Algorithm for a memory-based Viterbi decoder

ABSTRACT

An algorithm for a memory-based Viterbi decoder is disclosed in the invention, which employs the property of a trace-back path; that is, the similarity between two consecutive trace-back paths becomes higher as the data error rate goes down. Therefore, the algorithm of the invention is to save the previous trace-back path into a register, and as soon as the current trace-back path is found to be the same as the previous one, the demanded path is obtained. After that, the memory read operations will stop, and thus the power consumption made by the memory read operations would be largely reduced. Besides, before the path trace-back, the path prediction can be executed by utilizing the property that the minimum path metric and the path are consecutive. In conclusion, the invention is capable of reducing the number of memory access operations and the power consumption by employing the mechanisms of path matching and path prediction.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to an algorithm for a memory-based Viterbidecoder and, more particularly, to an algorithm for a Viterbi decoderthat applies the mechanisms of path matching and path prediction.

[0003] 2. Description of the Related Art

[0004] Error correction codes have been playing a key role in datatransmission because adding them into digitalized data has been a mustto ensure the correctness of data transmission. In general, errorcorrection codes can be classified into two categories. One category isa block code, which employs a method to encode data per block, and thereis no time relation between each block. The other category is aconvolutional code, which, unlike the block code, has time relationexisting in the encoding process.

[0005] The most common method applied to a convolutional code decoder isthe Viterbi algorithm, which is also the most effective decodingalgorithm for the convolutional code. A decoder that employs suchalgorithm is called the Viterbi decoder. During the decoding process,the existing architecture must decode a certain length of data, despitethe data is correct or incorrect, in order to obtain a correct data. Thelength of data is called a truncation length. During the decoding, alarge quantity of memory bandwidth and a large number of memory accessoperations are required. As for real applications, usually a decodingthat is smaller than the truncation length is good enough for judgingthe precision of data. For this reason, a lot of power is wasted duringmemory access.

[0006] To illustrate the redundant power consumption, the U.S. Pat. No.5,208,816 will be illustrated as an example. This prior art provides amemory algorithm for a high-speed Viterbi decoder, which transmitsparity checking code for inspecting the Viterbi decoder and determiningdata reliability. When unreliable data has been detected, the secondround of Viterbi estimation or retransmission will be executed toincrease data precision. However, the method is only suitable forlow-speed transmission. Besides, because a conventional Viterbi decoderrequires a lot of memory bandwidth, the low power consumption is hard tobe achieved. Moreover, another U.S. Pat. No. 4,905,317 is alsodisclosed, which is to synthesize the states when executing the pathtrace-back operation for obtaining a jumping back effect so that thememory access operations can be decreased as well as the decoding speedcan be increased. Unfortunately, even though the decoding speed has beenincreased, it cannot satisfy the current demand for decoding speed whenapplication is involved. Besides, the paths that have been traced backby jumping back have to be figured out again when executing the nextdecoding because the data in these paths is probably a solution on thenext decoding, which in turn will demand a lot of redundant calculationsand memory read operations.

[0007] Therefore, the invention provides an algorithm for a memory-basedViterbi decoder, which employs the mechanisms of path matching and pathprediction so as to reduce the number of memory access operations andthe power consumption so that the aforementioned drawback lying in theprior art can be improved.

SUMMARY OF THE INVENTION

[0008] The main and first object of the invention is to provide analgorithm for a memory-based Viterbi decoder, which can predict thepossible correct path while concurrently calculating the path metrics sothat the number of memory access operations can be reduced during thesubsequent decoding process; meanwhile, the truncation length requiredby the decoding can be dynamically adjusted in accordance with themechanism of path merging according to the different error probabilitiesso that the power consumption made by the memory access operationsduring the decoding process can be reduced.

[0009] The second object of the invention is to provide an algorithm fora memory-based Viterbi decoder, which can dynamically adjust thequantity of memory access operations during the decoding processaccording to the received state of data so that redundant calculationsin the real applications can be discarded by employing the property ofthe received data codes in the error correction circuit in order toeffectively reduce the power consumption of the circuits in the realoperation.

[0010] The third object of the invention is to provide an algorithm fora memory-based Viterbi decoder, which can largely reduce the memory readoperations so that a high-speed application with low power consumptioncan be achieved.

[0011] The fourth object of the invention is to provide a simple methodfor achieving the low power consumption so that the method can be costcompetitive as well as application competitive.

[0012] The algorithm of the invention includes the following procedures:first, to calculate each path according to the inputted data; second, tocalculate each path metric and obtain a minimum path metric aftercomparing the path metrics so as to find the state of the minimum pathmetric, and when the state of the minimum path metric is found to belocated on a consecutive path, it means that the consecutive path is thepredicted trace-back path; and finally, to find a merging pointaccording to the predicted trace-back path while executing thetrace-back path procedure, so that the decoding process can be proceededto obtain a decoding signal.

[0013] Also, the aforementioned path prediction procedure furtherincludes the following steps: first, to find the state of the minimumpath metric at the time t; second, if the state transition sequence fromthe time t−1 to the time t is located within the trellis, the state ofthe minimum path metric of the time t will be saved in a register;third, to predict the time t+1 and save the calculated state in theregister and then combine the calculated state with the state of thetime t; and finally, the path prediction procedure will stop when thestate of the minimum path metric are not located on a consecutive path.In particular, if the path saved in the register is ensured to becorrect, the decoding process will be based on the register access.

[0014] Moreover, the path matching procedure can be executedconcurrently while executing the path trace-back procedure. The pathmatching procedure includes the following steps: first, to save thetrace-back path of the previous moment to the register; next, to comparethe current trace-back path to the previous trace-back path; and last,when the two paths are merged, the demanded path can be obtained fromthe register, and the subsequent decoding process will be executed byusing the register.

[0015] The objects and technical contents of the invention will bebetter understood through the description of the following embodimentswith reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a schematic diagram showing the Viterbi decoder beingapplied to a wireless local area network.

[0017]FIG. 2 is a schematic diagram showing the architecture of theViterbi decoder of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The method of path trace-back is suitable for the Viterbi decoderwith large number of states but low power consumption. However, as thedemand for higher decoding speed increases, the demand for the bandwidthof the whole memory will become greater, which in turn will increase thepower consumption made by the memory access. In addition, it is obviousthat the similarity between two consecutive trace-back paths will becomehigher as the data error rate goes down. When in real application, thebit error rate (BER) of the inputted data will be around 10⁻², andninety-five percent of the trace-back paths will be similar at thistime. For this reason, the invention applies the above-mentionedproperties as well as the mechanisms of path matching and pathprediction so that up to seventy-five percent of the number of memoryread operations can be eliminated, and the power consumption can bereduced as well.

[0019]FIG. 1 is a schematic diagram showing the Viterbi decoder isapplied to an IEEE 802.11a wireless local area network. As shown in FIG.1, after the RF receiver 10 has received the radio frequency signals,the following procedures will be executed sequentially: first, thesynchronizer 12 will synchronize the signals; second, the demodulator ofthe orthogonal frequency division multiplexing (OFDM) 14 will demodulatethe signals; third, the channel calibrator 16 will calibrate thesignals; fourth, the demapper 18 will demap each formatting code; fifth,the deinterleaver 20 will restore the data that has been interleaved todifferent symbols to its original place; and finally, the data will betransmitted to a Viterbi decoder 22 for decoding the convolutional codeso as to rectify the data error generated during the transmission.

[0020] During Viterbi decoder's decoding of the convolutional code, onlya decoded code length that is smaller than the truncation length will berequired to determine the correct data. Therefore, the invention iscapable of predicting the possible correct path concurrently whilecalculating the path metrics under the memory-based architecture so thatthe number of memory access operations can be reduced during thesubsequent decoding process.

[0021]FIG. 2 is a schematic diagram showing the architecture of theViterbi decoder of the invention, which is to illustrate the detailsteps contained in the algorithm to be applied to the memory-basedViterbi decoder 22. As shown in FIG. 2, the detailed steps are: first, atransition metric unit (TMU) 24 will calculate branch metrics accordingto the inputted data; second, the branch metrics will be transmitted toan add-compare-select unit (ACSU) 26 for path metrics calculation andpath selection; third, the derived path will be stored in the survivormemory unit 28 (SMU); fourth, each path metric will be obtained througha path metric memorizing unit 30, and then the comparator 32 willcompare the path metrics and derive a trace-back starting point to betransmitted to a decoder 34; finally, the decoder 34 will perform pathtrace-back by reading the required data from the survivor memory unit 28and continue with the decoding.

[0022] During the path calculation, the path prediction 36 can beexecuted concurrently, which is to find the state of the minimum pathmetric according to the path metrics. Then, the next step is to judgewhether the state of the minimum path metric is located on a consecutivepath. And in order to complete the judgment, the state of the minimumpath metric at the time t must be found first. When the state transitionsequence from the time t−1 to the time t is found to be located in thetrellis, the state of the minimum path metric at the time t will besaved in a register 38 located inside the survivor memory unit 28 foradjusting the memory access during the decoding. Afterwards, theprediction of time t+1 will be performed, and its state will be saved inthe register 38 and merged with the state value of time t. Inparticular, the prediction can be consecutively executed between theadjacent time points, and if the states of the minimum path metrics arelocated on the same consecutive path, it means that the consecutive pathis the desired trace-back path. Conversely, if the values are found notlocating on a consecutive path, the prediction procedure will stop. Assoon as the prediction of trace-back path has been done, the decoder 34will find a merging point to proceed with the decoding according to thetrace-back path so as to obtain the demanded decoding signal withoutdecoding to the truncation length.

[0023] If the trace-back path has been correctly predicted, it meansthat the path stored in the register 38 is correct, and thus thedecoding will be executed by accessing the register 38.

[0024] In addition to executing the path prediction 36, the pathmatching can be performed concurrently or separately. The path matchingis first to store the trace-back path calculated at the previous momentinto the register 38 and then calculate the trace-back path at thecurrent moment. Next, the two trace-back paths at the previous momentand the current moment will be compared, and when the two paths arefound merged, the demanded path is obtained.

[0025] The algorithm of the invention can be implemented throughsoftware, multiprocessor, or digital signal processor. Besides, themethod provided in the invention is to associate the property of pathback-trace with the reliability of the inputted data of the Viterbialgorithm. Therefore, the trace-back path can be stored in the registerso that there is a good chance to directly use the path in the registerat the next trace-back and thus eliminate most of the memory readoperations. Moreover, the invention decides the memory read operation onthe basis of the reliability of inputted data so that the bandwidthratio of the memory writing to the memory reading can approximatelyreach a ratio of 1:1. Finally, the Viterbi decoder can appropriatelyadjust the decoding calculations according to the accuracy of theinputted data, which certainly will be a plus to the efficiency of theViterbi decoder.

[0026] In conclusion, the invention can dynamically adjust the quantityof memory access operations during the decoding process according to thestate of the received data so that the redundant calculations can beeliminated in the error correction circuit in the real application byutilizing the property of the received data codes. Therefore, when thecircuits are in real operation, the number of memory access operationsand the power consumption can be reduced, which in turn can achieve ahigh-speed application with low power consumption. Hence, the inventionis able to achieve low-power consumption with a simple method, which inturn proves that the invention can be very competitive in cost savingand practical application.

[0027] The embodiments above are only intended to illustrate theinvention; they do not, however, to limit the invention to the specificembodiments. Accordingly, various modifications and changes may be madewithout departing from the spirit and scope of the invention asdescribed in the appended claims.

What is claimed is:
 1. An algorithm for a memory-based Viterbi decoder,including the following procedures: to calculate a path according to theinputted data; to calculate each path metric and obtain a minimum pathmetric by comparing the path metrics so as to find the state of theminimum path metric; to judge whether the state of the minimum pathmetric is located on a consecutive path, and if so, it means that theconsecutive path is the predicted trace-back path; otherwise, theprediction will be stopped; and to find a merging point to execute thedecoding process according to the predicted trace-back path during thepath trace-back procedure so as to get a decoded signal.
 2. Thealgorithm for a memory-based Viterbi decoder as claimed in claim 1,wherein the minimum path metric can be utilized to predict the pathconcurrently while executing the path calculation.
 3. The algorithm fora memory-based Viterbi decoder as claimed in claim 1, wherein during thedecoding of the predicted trace-back path, the length of the predictedtrace-back path is smaller than that of the decoding of a truncationlength.
 4. The algorithm for a memory-based Viterbi decoder as claimedin claim 1, wherein the procedure of judging that whether the state ofthe minimum path metric is located on a consecutive path furtherincludes the following steps: to find the state of the minimum pathmetric at the time t; to save the state of the minimum path metric ofthe time t in a register if the state transition sequence from the timet−1 to the time t is located within the trellis; and to predict the timet+1, to save the calculated state in the register, and to combine thecalculated state with the state of the time t; the path predictionprocedure will stop as soon as the states of the minimum path metricsafter combination are found not to be located on a consecutive path. 5.The algorithm for a memory-based Viterbi decoder as claimed in claim 4,wherein if the path saved in the register is correct, the decodingprocess will be based on the register access.
 6. The algorithm for amemory-based Viterbi decoder as claimed in claim 1, wherein the pathmatching procedure can be executed concurrently while executing the pathprediction procedure, and the path matching procedure further comprisesthe following steps: to save the trace-back path of the previous momentto the register; and to compare the current trace-back path to theprevious trace-back path, and when the two trace-back paths are merged,the demanded path can be obtained.
 7. The algorithm for a memory-basedViterbi decoder as claimed in claim 6, wherein if the path saved in theregister is correct, the decoding process will be based on the registeraccess.
 8. The algorithm for a memory-based Viterbi decoder as claimedin claim 4 or claim 6, wherein the register is provided inside thesurvivor memory unit of the Viterbi decoder to adjust the memory accessduring the decoding process.
 9. The algorithm for a memory-based Viterbidecoder as claimed in claim 1, wherein the algorithm can be implementedthrough software, multiprocessor, or digital signal processor.
 10. Analgorithm for a memory-based Viterbi decoder, including the followingprocedures: to calculate a path according to the inputted data; tocalculate each path metric and obtain the minimum path metric bycomparing the path metrics so as to find the state of the minimum pathmetric; to judge whether the state of the minimum path metric is locatedon a consecutive path, and if so, it means that the consecutive path isthe predicted trace-back path; otherwise, the prediction will bestopped; to save the trace-back path of the current moment into aregister; to find a merging point to execute the decoding processaccording to the predicted trace-back path during the path trace-backprocedure so as to get a decoded signal; and to calculate the currenttrace-back path and compare the current trace-back path to the previoustrace-back path; when the two paths are merged, the demanded path isderived, and the subsequent decoding procedure can be executed.
 11. Thealgorithm for a memory-based Viterbi decoder as claimed in claim 10,wherein the minimum path metric can be utilized to predict the pathconcurrently while executing the path calculation.
 12. The algorithm fora memory-based Viterbi decoder as claimed in claim 10, wherein duringthe decoding of the predicted trace-back path, the length of thepredicted trace-back path is smaller than that of the decoding of atruncation length.
 13. The algorithm for a memory-based Viterbi decoderas claimed in claim 10, wherein the procedure of judging that whetherthe state of the minimum path metric is located on a consecutive pathfurther includes the following steps: to find the state of the minimumpath metric at the time t; to save the state of the minimum path metricof the time t in a register if the state transition sequence from thetime t−1 to the time t is located within the trellis; and to predict thetime t+1, to save the calculated state in the register, and to merge thecalculated state with the state of the time t; the path predictionprocedure will stop as soon as the states of the minimum path metricsafter merging are found to be located on a consecutive path.
 14. Thealgorithm for a memory-based Viterbi decoder as claimed in claim 10 orclaim 13, wherein if the path saved in the register is correct, thedecoding process will be based on the register access.
 15. The algorithmfor a memory-based Viterbi decoder as claimed in claim 10, wherein theregister is provided inside the survivor memory unit of the Viterbidecoder to adjust the memory access during the decoding process.
 16. Thealgorithm for a memory-based Viterbi decoder as claimed in claim 10,wherein the algorithm can be implemented through software,multiprocessor, or digital signal processor.